Field of the Invention
The present invention relates to high density memory devices, and particularly the operation of flash memory devices.
Description of Related Art
Memory technologies used for integrated circuit memories are being developed at smaller and smaller technology nodes, and are being deployed on larger and larger memory arrays on a single integrated circuit. Technologies being pursued include multiple layers of memory cells on a single chip. Operations performed on a 3D (three-dimensional) flash memory having multiple layers of memory cells include read, write and erase.
A flash memory is usually configured so that it can be erased a block at a time by a block erase. When a block is erased, memory cells in the block are set to one logic value, such as “1”. After a block is erased, memory cells in the block can be programmed to a different value, such as “0”. Once a memory cell is programmed to “0”, the memory cell can be changed back to “1” by a block erase of the block including the programmed memory cell. Once some memory cells in a block, such as cells in a selected byte or word in the block, are programmed to “0” during a first program operation, other memory cells in a different byte or word in the same block that are known to be in the erased state, can still be programmed to “0” during a second program operation without requiring a pre-erase of the block.
However, a general issue of high density flash memories is that the size of a block of memory cells is often very large. This is not convenient if a pre-erase of the block is required every time a single memory cell in the block that has been programmed to “0” needs to be changed back to “1”. As the density of flash memories increases, the number of layers in the stacks increase, leading to larger block sizes and further inconvenience in erase operations.
Thus, it is desirable to provide for a technology that allows multiple write operations to change a same memory cell from one logic value to a different logic value and vice versa after each erase operation.